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19-3109; Rev 1; 3/09
315MHz/434MHz ASK Superheterodyne Receiver
General Description
The MAX7034 fully integrated low-power CMOS superheterodyne receiver is ideal for receiving amplitudeshift-keyed (ASK) data in the 300MHz to 450MHz frequency range (including the popular 315MHz and 433.92MHz frequencies). The receiver has an RF sensitivity of -114dBm. With few external components and a low-current power-down mode, it is ideal for cost-sensitive and power-sensitive applications typical in the automotive and consumer markets. The MAX7034 consists of a low-noise amplifier (LNA), a fully differential image-rejection mixer, an on-chip phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO), a 10.7MHz IF limiting amplifier stage with received-signal-strength indicator (RSSI), and analog baseband data-recovery circuitry. The MAX7034 is available in a 28-pin (9.7mm x 4.4mm) TSSOP package and is specified over the automotive (-40C to +125C) temperature range.
PART
Features
o Optimized for 315MHz or 433.92MHz Band o Operates from Single +5.0V Supply o Selectable Image-Rejection Center Frequency o Selectable x64 or x32 fLO/fXTAL Ratio o Low (< 6.7mA) Operating Supply Current o < 3.0A Low-Current Power-Down Mode for Efficient Power Cycling o 250s Startup Time o Built-In 44dB RF Image Rejection o Excellent Receive Sensitivity Over Temperature o -40C to +125C Operation
MAX7034
Ordering Information
TEMP RANGE -40C to +125C PIN-PACKAGE 28 TSSOP MAX7034AUI/V+T
Applications
Automotive Remote Keyless Entry Security Systems Garage Door Openers Home Automation Remote Controls Local Telemetry Wireless Sensors
/Vdenotes an automotive qualified part. +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
Pin Configuration
TOP VIEW
XTAL1 1 AVDD 2 LNAIN 3 LNASRC 4 AGND 5 LNAOUT 6 AVDD 7 MIXIN1 8 MIXIN2 9 AGND 10 IRSEL 11 MIXOUT 12 DGND 13 DVDD 14
Typical Application Circuit appears at end of data sheet.
+
28 XTAL2 27 SHDN 26 PDOUT 25 DATAOUT
MAX7034
24 VDD5 23 DSP 22 DFFB 21 OPP 20 DSN 19 DFO 18 IFIN2 17 IFIN1 16 XTALSEL 15 EN_REG
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
315MHz/434MHz ASK Superheterodyne Receiver MAX7034
ABSOLUTE MAXIMUM RATINGS
VDD5 to AGND.......................................................-0.3V to +6.0V AVDD to AGND ......................................................-0.3V to +4.0V DVDD to DGND......................................................-0.3V to +4.0V AGND to DGND.....................................................-0.1V to +0.1V IRSEL, DATAOUT, XTALSEL, SHDN, EN_REG to AGND ....................-0.3V to (VDD5 + 0.3V) All Other Pins to AGND............................-0.3V to (DVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 12.8mW/C above +70C) ..1025.6mW Operating Temperature Range .........................-40C to +125C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VDD5 = +4.5V to +5.5V, no RF signal applied. TA = -40C to +125C, unless otherwise noted. Typical values are at VDD5 = +5.0V and TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Supply Voltage Supply Current Shutdown Supply Current Input-Voltage Low SYMBOL VDD5 IDD ISHDN VIL EN_REG, SHDN Input-Voltage High VIH XTALSEL Input Logic Current High IIH fRF = 434MHz, VIRSEL = DVDD Image-Reject Select Voltage (Note 2) fRF = 375MHz, VIRSEL = DVDD/2 fRF = 315MHz, VIRSEL = 0V DATAOUT Output-Voltage Low DATAOUT Output-Voltage High VOL VOH ISINK = 10A ISOURCE = 10A 0.125 VDD5 0.125 DVDD 0.4 1.1 DVDD 1.5 0.4 V V V VDD5 0.4 DVDD 0.4 15 V CONDITIONS +5.0V nominal supply voltage VSHDN = VDD5 VSHDN = 0V fRF = 315MHz fRF = 434MHz MIN 4.5 TYP 5.0 6.7 7.2 3 MAX 5.5 8.2 8.7 8 0.4 UNITS V mA A V
A
2
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315MHz/434MHz ASK Superheterodyne Receiver
AC ELECTRICAL CHARACTERISTICS
(Typical Application Circuit, VVDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50, fRF = 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VVDD5 = +5.0V and TA = +25C.) (Note 1)
PARAMETER GENERAL CHARACTERISTICS Startup Time Receiver Input Frequency Range Maximum Receiver Input Level Sensitivity at TA = +25oC (Note 3) Sensitivity at TA = +125C (Note 3) Maximum Data Rate LNA/MIXER LNA/Mixer Voltage Gain (Note 4) LNA/Mixer Input-Referred 1dB Compression Point Mixer Output Impedance Mixer Image Rejection INTERMEDIATE FREQUENCY (IF) Input Impedance Operating Frequency 3dB Bandwidth RSSI Linearity RSSI Dynamic Range RSSI Level PRFIN < -120dBm PRFIN > -40dBm ZIN_IF fIF Bandpass response 330 10.7 10 0.5 80 1.15 2.2 MHz MHz dB dB V ZOUT_MIX fRF = 434MHz, VIRSEL = DVDD fRF = 375MHz, VIRSEL = DVDD/2 fRF = 315MHz, VIRSEL = 0V 330 IF filter load 45 -50 330 42 44 44 dB dB dBm +25C, 315MHz +25C, 434MHz +125C, 315MHz +125C, 434MHz Manchester coded NRZ coded tON fRF Time for valid signal detection after VSHDN = VDD5. Does not include baseband filter settling. 300 0 -114 -113 -113 -110 33 66 250 450 s MHz dBm dBm dBm kbps SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX7034
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
AC ELECTRICAL CHARACTERISTICS (continued)
(Typical Application Circuit, VVDD5 = +4.5V to +5.5V, all RF inputs are referenced to 50, fRF = 433.92MHz, TA = -40C to +125C, unless otherwise noted. Typical values are at VVDD5 = +5.0V and TA = +25C.) (Note 1)
PARAMETER DATA FILTER Maximum Bandwidth DATA SLICER Comparator Bandwidth Maximum Load Capacitance Output High Voltage Output Low Voltage CRYSTAL OSCILLATOR fRF = 433.92MHz Crystal Frequency (Note 5) fXTAL fRF = 315MHz Crystal Tolerance Input Capacitance From each pin to ground VXTALSEL = 0V VXTALSEL = DVDD VXTALSEL = 0V VXTALSEL = DVDD 6.6128 13.2256 4.7547 9.5094 50 6.2 ppm pF MHz CLOAD 100 10 VVDD5 0 kHz pF V V 50 kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 1: 100% tested at TA = +125C. Guaranteed by design and characterization over entire temperature range. Note 2: IRSEL is internally set to 375MHz IR mode. It can be left open when the 375MHz image-rejection setting is desired. Bypass to AGND with a 1nF capacitor in a noisy environment. Note 3: Peak power level. BER = 2 x 10-3, Manchester encoded, data rate = 4kbps, IF bandwidth = 280kHz. Note 4: The voltage conversion gain is measured with the LNA input matching inductor and the LNA/Mixer resonator in place, and does not include the IF filter insertion loss. Note 5: Crystal oscillator frequency for other RF carrier frequency within the 300MHz to 450MHz range is (fRF - 10.7MHz)/64 for XTALSEL = 0V, and (fRF - 10.7MHz)/32 for XTALSEL = DVDD.
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315MHz/434MHz ASK Superheterodyne Receiver
Typical Operating Characteristics
(Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25C, unless otherwise noted.)
BIT-ERROR RATE vs. PEAK RF INPUT POWER
MAX7034 toc02
MAX7034
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX7034 toc01
SUPPLY CURRENT vs. RF FREQUENCY
9.0 8.5 SUPPLY CURRENT (mA) 8.0 7.5 7.0 6.5 6.0 5.5 5.0 -40C 0.01 250 300 350 400 450 RF FREQUENCY (MHz) 500 -130 +25C +125C +105C +85C 100.00
433.92MHz 10.00 BIT-ERROR RATE (%)
7.6 SUPPLY CURRENT (mA) 7.4 7.2 7.0 6.8 6.6 4.5 4.7 4.9 5.1 5.3 SUPPLY VOLTAGE (V) +85C +105C +125C
1.00
+25C
315MHz 0.10
-40C
5.5
-125 -120 -115 PEAK RF INPUT POWER (dBm)
-110
SENSITIVITY vs. TEMPERATURE
MAX7034 toc04
RSSI vs. RF INPUT POWER
MAX7034 toc05
RSSI AND DELTA vs. IF INPUT POWER
2.40 2.20 2.00 RSSI (V) 1.80 1.60 1.40 1.20 1.00 DELTA -5 -10
MAX7034 toc06
-102 -104 -106 SENSITIVITY (dBm) -108 -110 -112 -114 -116 -118 -120 -40 -15 10 35 60 85 TEMPERATURE (C) 110 315MHz 433.92MHz
2.40 2.20 2.00 RSSI (V) 1.80 1.60 1.40 1.20 1.00 -140 -120 -100 -80 -60 -40 RF INPUT POWER (dBm) -20 0 IF BANDWIDTH = 280kHz
RSSI
MAX7034 toc03
7.8
15 10 5 0 DELTA
-15 -20 -25 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 IF INPUT POWER (dBm) 10
LNA/MIXER VOLTAGE GAIN vs. IF FREQUENCY
MAX7034 toc07
IMAGE REJECTION vs. RF FREQUENCY
MAX7034 toc08
IMAGE REJECTION vs. TEMPERATURE
MAX7034 toc09
65 UPPER SIDEBAND 55 LNA/MIXER VOLTAGE GAIN (dB) 45 35 25 15 LOWER SIDEBAND 5 -5 0 5 10 15 20 IF FREQUENCY (MHz) 25 49.7dB IMAGE REJECTION
60 fRF = 315MHz 50 IMAGE REJECTION (dB) 40 30 20 10 0 fRF = 433.92MHz
52 50 IMAGE REJECTION (dB) 48 46 44 42 40 433.92MHz
315MHz
30
280 300 320 340 360 380 400 420 440 460 480 RF FREQUENCY (MHz)
-40
-15
10 35 60 85 TEMPERATURE (C)
110
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Typical Operating Characteristics (continued)
(Typical Application Circuit, VDD5 = +5.0V, fRF = 433.92MHz, TA = +25C, unless otherwise noted.)
NORMALIZED IF GAIN vs. IF FREQUENCY
MAX7034 toc10
S11 MAGNITUDE PLOT OF RFIN vs. FREQUENCY
MAX7034 toc11
S11 SMITH CHART PLOT OF RFIN
MAX7034 toc12
5 0 NORMALIZED IF GAIN (dB) -5 -10 -15 -20 -25 -30 1 10 IF FREQUENCY (MHz)
50 40 30 S11 MAGNITUDE (dB) 20 10 0 -10 -20 -30 -40 -50 315MHz -24.1dB
500MHz
WITH INPUT MATCHING
315MHz 200MHz
100
200 230 260 290 320 350 380 410 440 470 500 FREQUENCY (MHz)
PHASE NOISE vs. OFFSET FREQUENCY
MAX7033 toc13
PHASE NOISE vs. OFFSET FREQUENCY
fRF = 433.92MHz -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 -140
MAX7033 toc14
0 fRF = 315MHz -20 PHASE NOISE (dBc/Hz) -40 -60 -80 -100 -120 -140 10 100 1k 10k 100k 1M
0
10M
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
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315MHz/434MHz ASK Superheterodyne Receiver
Pin Description
PIN 1 2, 7 3 4 5, 10 6 8 9 NAME XTAL1 AVDD LNAIN LNASRC AGND LNAOUT MIXIN1 MIXIN2 Crystal Input 1 Positive Analog Supply Voltage. AVDD is connected to an on-chip +3.4V low-dropout regulator. Both AVDD pins must be externally connected to each other. Bypass pin 2 to AGND with a 0.1F capacitor as close as possible to the pin (see the Typical Application Circuit). Bypass pin 7 with a 0.01F capacitor. Low-Noise Amplifier Input. See the Low-Noise Amplifier section. Low-Noise Amplifier Source for external Inductive Degeneration. Connect inductor to ground to set LNA input impedance. See the Low-Noise Amplifier section. Analog Ground Low-Noise Amplifier Output. Connect to mixer input through an LC tank filter. See the Low-Noise Amplifier section. 1st Differential Mixer Input. Connect to LC tank filter from LNAOUT through a 100pF capacitor. See the Typical Application Circuit. 2nd Differential Mixer Input. Connect to AVDD side of the LC tank filter through a 100pF capacitor. See the Typical Application Circuit. Image-Rejection Select. Set VIRSEL = 0V to center image rejection at 315MHz. Leave IRSEL unconnected to center image rejection at 375MHz. Set VIRSEL = DVDD to center image rejection at 434MHz. See the Mixer section. 330 Mixer Output. Connect to the input of the 10.7MHz bandpass filter. Digital Ground Positive Digital Supply Voltage. Connect to AVDD. Bypass to DGND with a 0.01F capacitor as close as possible to the pin. Regulator Enable. Connect to VDD5 to enable internal regulator. Pull this pin low to allow device operation between +3.0V and +3.6V. See the Voltage Regulator section. Crystal Divider Ratio Select. Drive XTALSEL low to select divider ratio of 64, or drive XTALSEL high to select divider ratio of 32. 1st Differential Intermediate-Frequency Limiter Amplifier Input. Connect to the output of a 10.7MHz bandpass filter. 2nd Differential Intermediate-Frequency Limiter Amplifier Input. Bypass to AGND with a 1500pF capacitor as close as possible to the pin. Data Filter Output Negative Data Slicer Input Noninverting Op-Amp Input for the Sallen-Key Data Filter Data Filter Feedback Node. Input for the feedback of the Sallen-Key data filter. Positive Data Slicer Input +5.0V Supply Voltage Digital Baseband Data Output Peak-Detector Output Power-Down Select Input. Drive high to power up the IC. Internally pulled down to AGND with a 100k resistor. Crystal Input 2. Can also be driven with an external reference oscillator. See the Crystal Oscillator section. FUNCTION
MAX7034
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
IRSEL MIXOUT DGND DVDD EN_REG XTALSEL IFIN1 IFIN2 DFO DSN OPP DFFB DSP VDD5 DATAOUT PDOUT SHDN XTAL2
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Functional Diagram
LNASRC 4 EN_REG LNAOUT 15 6 MIXIN1 MIXIN2 8 9 IRSEL 11 MIXOUT 12 IFIN1 17 IFIN2 18
LNAIN
3
0 LNA Q IMAGE REJECTION 90 I MAX7034 RSSI
IF LIMITING AMPS
AVDD VDD5 DVDD
2, 7 24 3.4V REG
14
DIVIDE BY 64 PHASE DETECTOR /1
VCO RDF2 100k LOOP FILTER CRYSTAL DRIVER 1 28 POWERDOWN 27 SHDN 25 DATAOUT DATA SLICER
DATA FILTER RDF1 100k
DGND
13
AGND
5, 10
/2
16 XTALSEL
20
23
19
26 PDOUT
21 OPP
22 DFFB
XTAL1 XTAL2
DSN DSP DFO
Detailed Description
The MAX7034 CMOS superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. Depending on signal power and component selection, data rates can be as high as 33kbps Manchester (66kbps NRZ). The MAX7034 is designed to receive binary ASK data modulated in the 300MHz to 450MHz frequency range. ASK modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data.
Voltage Regulator
The MAX7034 is designed to work with a nominal +5.0V supply voltage. The MAX7034 integrates an internal voltage regulator that provides +3.4V to some of the internal circuits in the device; this voltage is connected to the AVDD and DVDD pins. The device can be operated from +3.0V to +3.6V by pulling the EN_REG pin low (which disables the internal voltage regulator) and connecting the supply voltage to the AVDD and DVDD pins. If the MAX7034 is powered from +3.0 to +3.6V, the performance is limited to the -40C to +105C range.
dependent on both the antenna matching network at the LNA input and the LC tank network between the LNA output and the mixer inputs. The off-chip inductive degeneration is achieved by connecting an inductor from LNASRC to AGND. This inductor sets the real part of the input impedance at LNAIN, allowing for a more flexible input impedance match, such as a typical printed-circuit board (PCB) trace antenna. A nominal value for this inductor with a 50 input impedance is 15nH, but is affected by the PCB trace. The LC tank filter connected to LNAOUT comprises L1 and C9 (see the Typical Application Circuit). Select L1 and C9 to resonate at the desired RF input frequency. The resonant frequency is given by: fRF = where: LTOTAL = L1 + LPARASITICS. CTOTAL = C9 + CPARASITICS. LPARASITICS and CPARASITICS include inductance and capacitance of the PCB traces, package pins, mixer input impedance, etc. These parasitics at high frequencies cannot be ignored, and can have a dramatic effect 1 2 L TOTAL x CTOTAL
Low-Noise Amplifier
The LNA is an nMOS cascode amplifier with off-chip inductive degeneration. The gain and noise figures are
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315MHz/434MHz ASK Superheterodyne Receiver
on the tank filter center frequency. The total parasitic capacitance is generally between 4pF and 6pF.
Mixer
A unique feature of the MAX7034 is the integrated image rejection of the mixer. This device eliminates the need for a costly front-end SAW filter for most applications. Advantages of not using a SAW filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. The mixer cell is a pair of double balanced mixers that perform an IQ downconversion of the RF input to the 10.7MHz IF from a low-side injected LO (i.e., fLO = fRF fIF). The image-rejection circuit then combines these signals to achieve 44dB of image rejection. Low-side injection is required due to the on-chip image-rejection architecture. The IF output is driven by a source follower biased to create a driving-point impedance of 330; this provides a good match to the off-chip 330 ceramic IF filter. The IRSEL pin is a logic input that selects one of the three possible image-rejection frequencies. When VIRSEL = 0V, the image rejection is tuned to 315MHz. VIRSEL = DV DD /2 tunes the image rejection to 375MHz, and VIRSEL = DVDD tunes the image rejection to 434MHz. The IRSEL pin is internally set to DVDD/2 (image rejection at 375MHz) when it is left unconnected, thereby eliminating the need for an external DVDD/2 voltage.
The RSSI circuit demodulates the IF by producing a DC output proportional to the log of the IF signal level, with a slope of approximately 14.2mV/dB.
MAX7034
Applications Information
Crystal Oscillator
The crystal oscillator in the MAX7034 is designed to present a capacitance of approximately 3pF between the XTAL1 and XTAL2. If a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its intended operating frequency, introducing an error in the reference frequency. Crystals designed to operate with higher differential load capacitance always pull the reference frequency higher. For example, a 4.7547MHz crystal designed to operate with a 10pF load capacitance oscillates at 4.7563MHz with the MAX7034, causing the receiver to be tuned to 315.1MHz rather than 315.0MHz, an error of about 100kHz, or 320ppm. It is very important to use a crystal with a load capacitance that is equal to the capacitance of the MAX7034 crystal oscillator plus PCB parasitics. In actuality, the oscillator pulls every crystal. The crystal's natural frequency is really below its specified frequency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. This pulling is already accounted for in the specification of the load capacitance. Additional pulling can be calculated if the electrical parameters of the crystal are known. The frequency pulling is given by: CM 1 1 x 106 C 2 CASE + CLOAD CCASE + CSPEC
Phase-Locked Loop
The PLL block contains a phase detector, charge pump, integrated loop filter, VCO, asynchronous 64x clock divider, and crystal oscillator driver. Besides the crystal, this PLL does not require any external components. The VCO generates a low-side LO. The relationship between the RF, IF, and reference frequencies is given by: f -f fREF = RF IF 32 x M where: M = 1 (VXTALSEL = DVDD) or 2 (VXTALSEL = 0V) To allow the smallest possible IF bandwidth (for best sensitivity), minimize the tolerance of the reference crystal.
fP =
where: fP is the amount the crystal frequency pulled in ppm. CM is the motional capacitance of the crystal. CCASE is the case capacitance. CSPEC is the specified load capacitance. CLOAD is the actual load capacitance. When the crystal is loaded as specified (i.e., CLOAD = CSPEC), the frequency pulling equals zero. It is possible to use an external reference oscillator in place of a crystal to drive the VCO. AC-couple the external oscillator to XTAL2 with a 1000pF capacitor. Drive XTAL2 with a signal level of approximately 500mVP-P. AC-couple XTAL1 to ground with a 1000pF capacitor.
9
Intermediate Frequency and RSSI
The IF section presents a differential 330 load to provide matching for the off-chip ceramic filter. The six internal AC-coupled limiting amplifiers produce an overall gain of approximately 65dB, with a bandpassfilter-type response centered near the 10.7MHz IF frequency with a 3dB bandwidth of approximately 10MHz.
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Data Filter
The data filter is implemented as a 2nd-order lowpass Sallen-Key filter. The pole locations are set by the combination of two on-chip resistors and two external capacitors. Adjusting the value of the external capacitors changes the corner frequency to optimize for different data rates. The corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. Keeping the corner frequency near the data rate rejects any noise at higher frequencies, resulting in an increase in receiver sensitivity. The configuration shown in Figure 1 can create a Butterworth or Bessel response. The Butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40dB/decade for the two-pole filter. The Bessel filter has a linear phase response, which works well for filtering digital data. To calculate the value of C5 and C6, use the following equations, along with the coefficients in Table 1: C5 = b a(100k)( )(fC ) slicing threshold, which is applied to the second comparator input. The suggested data slicer configuration uses a resistor (R1) connected between DSN and DSP with a capacitor (C4) from DSN to DGND (Figure 2). This configuration averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. With this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. The values of R1 and C4 affect how fast the threshold tracks to the analog amplitude. Be sure to keep the corner frequency of the RC circuit much lower than the lowest expected data rate. Note that a long string of zeros or ones can cause the threshold to drift. This configuration works best if a coding scheme, such as Manchester coding, which has an equal number of zeros and ones, is used. To prevent continuous toggling of DATAOUT in the absence of an RF signal due to noise, add hysteresis to the data slicer as shown in Figure 3.
a C6 = 4(100k)( )(fC ) where fC is the desired 3dB corner frequency. For example, to choose a Butterworth filter response with a corner frequency of 5kHz: C5 =
Table 1. Coefficents to Calculate C5 and C6
FILTER TYPE Butterworth (Q = 0.707) Bessel (Q = 0.577) a 1.414 1.3617 b 1.000 0.618
(1.414)(100k)(3.14)(5kHz)
1.000
450pF
MAX7034
RSSI RDF2 100k RDF1 100k
1.414 C6 = 225pF 4)(100k)(3.14)(5kHz) ( Choosing standard capacitor values changes C5 to 470pF and C6 to 220pF, as shown in the Typical Application Circuit.
Data Slicer
The data slicer takes the analog output of the data filter and converts it to a digital signal. This is achieved by using a comparator and comparing the analog input to a threshold voltage. One input is supplied by the data filter output. Both comparator inputs are accessible offchip to allow for different methods of generating the
19 DFO C6
21 OPP C5
22 DFFB
Figure 1. Sallen-Key Lowpass Data Filter
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Peak Detector
The peak-detector output (PDOUT), in conjunction with an external RC filter, creates a DC output voltage equal to the peak value of the data signal. The resistor provides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data-filter output voltage. For faster data slicer response, use the circuit shown in Figure 4. For more details on hysteresis and peak-detector applications, refer to Maxim Application Note 3671, Data Slicing Techniques for UHF ASK Receivers.
MAX7034
DATA SLICER
25 DATAOUT R1
23 DSP R3
20 DSN
R4
19 DFO
Layout Considerations
A properly designed PCB is an essential part of any RF/microwave circuit. On high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radiation. At high frequencies, trace lengths that are on the order of /10 or longer act as antennas. Keeping the traces short also reduces parasitic inductance. Generally, 1 inch of a PCB trace adds about 20nH of parasitic inductance. The parasitic inductance can have a dramatic effect on the effective inductance of a passive component. For example, a 0.5 inch trace connecting a 100nH inductor adds an extra 10nH of inductance or 10%. To reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. Also, use low-inductance connections to ground on all GND pins, and place decoupling capacitors close to all VDD connections.
R2
*OPTIONAL
C4
Figure 3. Generating Data Slicer Hysteresis
MAX7034
DATA SLICER
25 DATAOUT
20 DSN
23 DSP 25k
19 DFO
26 PDOUT
47nF
MAX7034
Figure 4. Using PDOUT for Faster Startup
DATA SLICER
25 DATAOUT
20 DSN R1
23 DSP
19 DFO
C4
Figure 2. Generating Data Slicer Threshold
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11
315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Typical Application Circuit
* C9 L1 L2 Y1 AT 315MHz DO NOT POPULATE 51nH 120nH 9.509375MHz AT 433.92MHz DO NOT POPULATE 27nH 56nH 13.225625MHz C14 15pF Y1 * C16 OPEN C15 15pF C19 OPEN F_IN
C18 OPEN +3.3V C7 100pF C12 0.1F
1 2
XTAL1 AVDD
XTAL2 SHDN
28 27 26 R2 OPEN TP4 C13 OPEN JU1
VDD 1 2 3 DSN 1 2 JU4 3 R5 10k VDD TP8 TP9 SHDN
RF_IN
L2 * L3 15nH
U1
3 4 5 LNAIN LNASRC AGND LNAOUT AVDD
PDOUT
MAX7034
+3.3V
C9 * +3.3V C2 0.01F C11 100pF
6 7
DATAOUT
25
DATA_OUT
L1 *
VDD5 8 MIXIN1 MIXIN2 DSP
24 C23 0.01F R7 0 C22 1000pF JU8 C24 0.1F C21 10pF
+3.3V C10 220pF
9 C8 100pF
23
GND
TP6 1 3
+3.3V 2 JU6
10 11
R6 OPEN
AGND IRSEL DFFB 22 C6 220pF DSN DSN 20 R1 5.1k MIXOUT DFO DGND DVDD IFIN2 18 19 C3 1500pF R8 10k C4 0.47F TP3 TP2 TP7 C5 470pF
+3.3V JU7
VDD VDD
OPP
21
TP5
C20 0.1F TP10
12 13 +3.3V C1 0.01F 14
17 IFIN1 16 XTALSEL TP12 EN_REG 15 VDD 1 TP11 3 Y2 10.7MHz IN 1 GND OUT 2 3 2 JU5 JU2 1 3
+3.3V 2
3 1
2 JU3
R3 OPEN
C17 OPEN
MIX_OUT
R4 OPEN
EN_REG
12
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315MHz/434MHz ASK Superheterodyne Receiver
Chip Information
PROCESS: CMOS
PACKAGE TYPE 28 TSSOP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE U28-1 DOCUMENT NO. 21-0066
MAX7034
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315MHz/434MHz ASK Superheterodyne Receiver MAX7034
Revision History
REVISION NUMBER 0 1 REVISION DATE 1/08 3/09 Initial release Added /V designation to part number. DESCRIPTION PAGES CHANGED -- 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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